Xử lý tín hiệu số với FPGA chương 2

ĐHBK Tp HCM BMĐT GV: Hồ Trung Mỹ Chapter 09
Algorithmic Strength Reduction in Filters and Transforms
(Giảm tính toán giải thuật trong
các bộ lọc và phép biến đổi) TLTK:
1. Các slide từ sách của Prof. Parhi
2. Slide của Prof. Lan-Da Van 1 Outline 9.1 Introduction 9.2 Parallel FIR Filters
9.3 Discrete Cosine Transform and Inverse DCT
9.4 Parallel Architectures for Rank-Order Filters 9.5 Conclusions 2 9.1 Introduction
• What is the strong operation
– Multiplication is strong compared to addition
• What is the algorithmic strength reduction
– Reduce the number of strong operations
– Exploits substructure sharing and leads to less silicon area of power consumption
• Advantage of the strength reduction?
– Enables design of parallel FIR filters with a less-than-linear increase in hardware
– Reduced area  reduced capacitance  low-power – Reduced multiplications – High speed Stre
ngth reduction leads to a reduction in hardware complexity by
exploiting substructure sharing. This transformation can lead to reduction
in silicon area or power consumption in a VLSI implementation or iteration·
period in a programmable DSP implementation. 3
Algorithm Strength Reduction 4