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SystemVerilog Complete Reference Algo Science Lab
Complete SystemVerilog Reference Guide
Comprehensive Coverage with Examples
Author: Shahrear Hossain Shawon
Algo Science Lab
1 Data Types
1.1 Logic and Bit Types
SystemVerilog provides 4-state (0,1,X,Z) and 2-state
(0,1) data types for hardware modeling.
1 // 4- state ty pes
2 log ic [7 :0] data ; // 8- bit
3 log ic s ign ed [15:0 ] s; // signe d
4 reg [3:0] o ld_st yle ; // leg ac y
5
6 // 2 - state type s
7 bit [7:0] f ast_d ata ; // fas te r simu lati on
8 byte s igne d_by te ; // 8- bit sign ed
9 s ho rt in t si ; // 16 - bit sign ed
10 int i ; // 32 - bit sign ed
11 long in t li ; // 64 - bit sign ed
1.2 Enumerated Types
Enumerations provide named values for better readabil-
ity and type safety.
1 type de f enum l ogic [1:0] {
2 IDLE = 2’ b00 ,
3 READ = 2’ b01 ,
4 WRITE = 2’b10 ,
5 ERROR = 2’ b11
6 } state _t ;
7
8 stat e_ t curre nt _st at e , n ext_ st ate ;
1.3 Structures and Unions
Structures group related data, unions save space by
overlapping members.
1 // S tr uc ture
2 type de f struct pack ed {
3 logic [ 7:0] opco de ;
4 logic [ 15 :0] addr ;
5 logic [ 31 :0] data ;
6 } ins truc tion _t ;
7
8 i nstr uct io n_t i nstr ;
9
10 // Unio n
11 type de f union pa cke d {
12 logic [ 31 :0] word ;
13 logic [ 15 :0] half [2];
14 logic [ 7:0] by te [4];
15 } data_u ;
1.4 Arrays
SystemVerilog supports packed, unpacked, dynamic,
associative, and queue arrays.
1 // Pac ke d a rray
2 log ic [ 7:0] [3 :0] pac ked_ ar r ;
3
4 // Un packe d array
5 log ic [7 :0] mem [0 :2 55 ];
6
7 // Dy na mi c ar ray
8 int dyn_ ar r [];
9 init ia l dyn_ ar r = new [1 0];
10
11 // A ss ocia tive array
12 int ass oc_ar r [ string ];
13
14 // Queu e
15 int queue [ $ ];
16 que ue . p us h_bac k (5) ;
2 Modules and Interfaces
2.1 Module with Parameters
Modules are the basic building blocks with optional pa-
rameters for configurability.
1 mo dul e ad der #(
2 pa ra meter WIDTH = 8
3 ) (
4 input logic [ WIDTH -1:0] a , b ,
5 input logic cin ,
6 outp ut l ogic [ WIDTH -1:0] sum ,
7 outp ut l ogic cout
8 ) ;
9 assi gn { cout , sum } = a + b + cin ;
10 e nd module
2.2 Interface
Interfaces encapsulate communication signals between
modules.
1 i nt erface axi_ if #(
2 pa ra meter AD DR_W ID TH = 32 ,
3 pa ra meter DA TA_W ID TH = 32
4 ) (
5 input l ogic clk , rs t_n
6 ) ;
7 logic [ ADDR_WID TH -1: 0] a wad dr ;
8 logic awvalid , awrea dy ;
9 logic [ DATA_WID TH -1: 0] wd ata ;
10 logic wvalid , wr ead y ;
11
12 mod po rt mast er (
13 outpu t awaddr , awvalid , wdata , wvalid ,
14 input awready , wread y
15 );
16
17 mod po rt slave (
18 input awaddr , awvalid , wdata , wvalid ,
19 outpu t awready , wread y
20 );
21 e ndin terf ace
2.3 Module with Interface
1 mo dul e axi _m aste r (
2 axi_ if . m as ter bus
3 ) ;
4 al wa ys_ff @( posedge bus . clk ) begin
5 if (! bus . rst_n )
6 bus . a wv al id <= 0;
7 else if ( bus . awre ad y )
8 bus . a wv al id <= 1;
9 end
10 e nd module
1
SystemVerilog Complete Reference Algo Science Lab
3 Sequential Logic
3.1 Always FF Blocks
Use always ff for synthesizable sequential logic.
1 mo dul e dff (
2 input logic clk , rst_n ,
3 input logic d ,
4 outp ut l ogic q
5 ) ;
6 al wa ys_ff @( posedge clk or ne ge dg e rs t_n )
begin
7 if (! r st_n )
8 q <= 1’ b0 ;
9 else
10 q <= d;
11 end
12 e nd module
3.2 Counter Example
1 mo dul e count er #(
2 pa ra meter WIDTH = 8
3 ) (
4 input logic clk , rst_n , en ,
5 outp ut l ogic [ WIDTH -1:0] cou nt
6 ) ;
7 al wa ys_ff @( posedge clk or ne ge dg e rs t_n )
begin
8 if (! r st_n )
9 count <= ’0;
10 else if ( en )
11 count <= count + 1;
12 end
13 e nd module
4 Combinational Logic
4.1 Always Comb Blocks
Use always comb for combinational logic.
1 mo dul e mux4t o1 (
2 input logic [1 :0] sel ,
3 input logic [3 :0] in ,
4 outp ut l ogic out
5 ) ;
6 al ways _com b begin
7 case ( sel )
8 2’ b00 : out = in [0];
9 2’ b01 : out = in [1];
10 2’ b10 : out = in [2];
11 2’ b11 : out = in [3];
12 endc as e
13 end
14 e nd module
4.2 Priority and Unique
priority and unique provide synthesis and simulation
checks.
1 mo dul e decod er (
2 input logic [2 :0] in ,
3 outp ut l ogic [7:0] out
4 ) ;
5 al ways _com b begin
6 uniqu e case ( in )
7 3’ d0 : out = 8 ’ b000 00 00 1 ;
8 3’ d1 : out = 8 ’ b000 00 01 0 ;
9 3’ d2 : out = 8 ’ b000 00 10 0 ;
10 3’ d3 : out = 8 ’ b000 01 00 0 ;
11 3’ d4 : out = 8 ’ b000 10 00 0 ;
12 3’ d5 : out = 8 ’ b001 00 00 0 ;
13 3’ d6 : out = 8 ’ b010 00 00 0 ;
14 3’ d7 : out = 8 ’ b100 00 00 0 ;
15 endc as e
16 end
17 e nd module
5 State Machines
5.1 FSM with Enum
Finite state machines are fundamental in digital design.
1 mo dul e fsm (
2 input logic clk , rst_n ,
3 input logic start , done ,
4 outp ut l ogic busy
5 ) ;
6 typ ed ef e num logic [1 :0] {
7 IDLE , ACTIVE , WAIT , C OM PL ETE
8 } s ta te_ t ;
9
10 sta te _t state , next ;
11
12 // State r eg is te r
13 al wa ys_ff @( posedge clk or ne ge dg e rs t_n )
begin
14 if (! r st_n )
15 state <= IDLE ;
16 else
17 state <= next ;
18 end
19
20 // Nex t st ate l ogic
21 al ways _com b begin
22 next = state ;
23 case ( state )
24 IDLE : if ( start ) next = AC TI VE ;
25 ACT IVE : next = W AIT ;
26 WAIT : if ( done ) nex t = COMP LETE ;
27 CO MP LE TE : next = IDLE ;
28 endc as e
29 end
30
31 // Outpu t l ogic
32 assi gn bus y = ( state != I DLE ) ;
33 e nd module
6 Functions and Tasks
6.1 Functions
Functions return a single value and execute in zero sim-
ulation time.
1 f un ct io n aut om atic int par ity (
2 input l ogic [7:0] data
3 ) ;
4 pari ty = ^ data ; // XOR re duct io n
5 e ndfu ncti on
6
7 f un ct io n aut om atic l ogic [7:0] reve rs e (
8 input l ogic [7:0] in
9 ) ;
10 for ( int i =0; i <8; i ++)
11 reve rs e [i] = in [7 -i];
12 e ndfu nc tion
6.2 Tasks
Tasks can have multiple outputs and consume simula-
tion time.
1 task a ut omat ic re ad _m em (
2 input logic [7 :0] addr ,
3 outp ut l ogic [ 31 :0] data ,
4 ref logic [ 31: 0] mem []
5 ) ;
6 #10 data = mem [ addr ];
7 endt as k
8
2
SystemVerilog Complete Reference Algo Science Lab
9 task a ut omat ic wr it e_mem (
10 input l ogic [7:0] addr ,
11 input l ogic [31: 0] data ,
12 ref logic [ 31: 0] mem []
13 ) ;
14 #10 mem [ addr ] = data ;
15 endt as k
7 Assertions
7.1 Immediate Assertions
Checked immediately like a procedural statement.
1 mo dul e ass ert _e xam pl e (
2 input l ogic clk , rst_n ,
3 input l ogic req , gnt
4 ) ;
5 // Imm ed iate ass ertio n
6 al ways _com b begin
7 asser t (!( req && ! gnt ) || gnt )
8 else $err or ( " Gr ant with ou t requ est ");
9 end
10 e nd module
7.2 Concurrent Assertions
Checked based on clock edges, using sequences and
properties.
1 mo dul e sva _exa mp le (
2 input l ogic clk , rst_n ,
3 input l ogic req , gnt , done
4 ) ;
5 // Prop erty : grant fo ll ow s reque st
6 pro perty p_ re q_gnt ;
7 @( p os ed ge clk ) d is ab le iff (! rst_n )
8 req | -> ##[1: 3] gnt ;
9 en dpro pert y
10
11 asse rt pro pe rt y ( p_ re q_gn t )
12 else $ err or ( " Grant not rec ei ve d ");
13
14 // Sequ ence : done a fter grant
15 seq uence s_ gnt_ do ne ;
16 gnt ## [1 :5 ] done ;
17 en dseq uenc e
18
19 asse rt pro pe rt y (
20 @( p os ed ge clk ) d is ab le iff (! rst_n )
21 gnt | -> s_g nt _don e
22 );
23 e nd module
8 Constrained Random
8.1 Classes with Constraints
Object-oriented features for verification.
1 cla ss p ack et ;
2 rand bit [7 :0] addr ;
3 rand bit [ 15: 0] dat a;
4 rand bit [1 :0] p type ;
5
6 co ns trai nt c_ad dr {
7 addr insi de {[8 ’ h00 :8 ’ h7F ]};
8 }
9
10 co ns trai nt c_ty pe {
11 ptype dist {
12 2’ b00 := 40 ,
13 2’ b01 := 30 ,
14 2’ b10 := 20 ,
15 2’ b11 := 10
16 };
17 }
18
19 fun ction void dis pl ay () ;
20 $ di sp la y (" Addr =% h Data =% h Type =% b" ,
21 addr , data , ptype ) ;
22 en dfun ctio n
23 e nd cl as s
24
25 mo dul e test ;
26 ini ti al begin
27 packe t pkt = new () ;
28 repea t (5) begin
29 ass ert ( pkt . ra nd omize () );
30 pkt . d is pl ay () ;
31 end
32 end
33 e nd module
9 Coverage
9.1 Covergroups
Functional coverage to track test completeness.
1 mo dul e cove rag e_ex amp le (
2 input l ogic clk ,
3 input l ogic [2:0] opcode ,
4 input l ogic [7:0] data
5 ) ;
6 co ve rgro up cg @ ( po se dg e clk ) ;
7 cp_ opcod e : co verp oi nt opc od e {
8 bins add = {3 ’ b000 };
9 bins sub = {3 ’ b001 };
10 bins mul = {3 ’ b010 };
11 bins div = {3 ’ b011 };
12 bins oth ers = defa ul t ;
13 }
14
15 cp_d at a : co ve rpoi nt data {
16 bins low = { [0:63 ]};
17 bins mid = { [64: 191] };
18 bins high = {[ 19 2:25 5]};
19 }
20
21 cr oss_ op_d ata : cross cp_op code ,
cp_d at a ;
22 end group
23
24 cg cg_i ns t = new () ;
25 e nd module
10 Clocking Blocks
10.1 Synchronous Testbench
Clocking blocks provide synchronous drive and sample
timing.
1 i nt erface bus_ if ( in put l ogic clk ) ;
2 logic [ 7:0] da ta ;
3 logic valid , r eady ;
4
5 clo cking cb @( pose dg e clk );
6 defa ul t input #1 step outp ut #2;
7 outpu t data , vali d ;
8 input re ady ;
9 en dclo ckin g
10
11 mod po rt TB ( cloc ki ng cb );
12 e ndin terf ace
13
14 prog ra m test ( b us_ if . TB bus );
15 ini ti al begin
16 bus . cb . data <= 8 ’hAA ;
17 bus . cb . valid <= 1;
18 @( bus . cb );
19 wait ( bus . cb . ready == 1) ;
20 end
3
SystemVerilog Complete Reference Algo Science Lab
21 e ndpr og ram
11 Virtual Interfaces
11.1 Polymorphism in Verification
Virtual interfaces enable dynamic interface binding.
1 cla ss d riv er ;
2 vir tu al bus_ if vif ;
3
4 fun ction new ( vi rt ua l bus_if vif );
5 this . vif = vif ;
6 en dfun ctio n
7
8 task run () ;
9 fore ve r begin
10 @( vif . cb );
11 vif . cb . data <= $ ra nd om ;
12 vif . cb . valid <= 1;
13 @( vif . cb );
14 vif . cb . valid <= 0;
15 end
16 end ta sk
17 e nd cl as s
18
19 mo dul e top ;
20 logic clk ;
21 bus_ if bus ( clk ) ;
22
23 ini ti al begin
24 drive r drv = new ( bus );
25 fork
26 drv . run () ;
27 joi n_non e
28 end
29 e nd module
12 Parameterized Classes
12.1 Generic Components
1 cla ss qu eue #( type T = int );
2 T ite ms [ $ ];
3
4 fun ction void push (T item );
5 items . p us h_bac k ( item ) ;
6 en dfun ctio n
7
8 fun ction T pop () ;
9 retur n it ems . pop_ front () ;
10 en dfun ctio n
11
12 fun ction int size () ;
13 retur n it ems . size () ;
14 en dfun ctio n
15 e nd cl as s
16
17 // Usag e
18 que ue #( int ) in t_q = new () ;
19 que ue #( byte ) by te_ q = new () ;
13 Interprocess Communication
13.1 Mailbox
1 mo dul e ipc _exa mp le ;
2 mai lb ox #( int ) mbx = new () ;
3
4 ini ti al begin // Prod uc er
5 for ( int i =0; i <10; i ++) begin
6 mbx . put (i );
7 $ d is pl ay (" Sent : %0 d" , i );
8 #10;
9 end
10 end
11
12 ini ti al begin // Cons um er
13 int data ;
14 repea t (10) beg in
15 mbx . get ( data );
16 $ d is pl ay (" R ec eived : %0 d" , data ) ;
17 end
18 end
19 e nd module
13.2 Semaphore
1 mo dul e se ma pho re_e xam ple ;
2 se ma phore sem = new (1) ;
3
4 task a cc ess _res ourc e ( int id );
5 sem . get () ;
6 $ di sp la y (" Task %0 d a ccess ing " , id );
7 #20;
8 $ di sp la y (" Task %0 d done " , id );
9 sem . put () ;
10 end ta sk
11
12 ini ti al f ork
13 ac cess _re sour ce (1) ;
14 ac cess _re sour ce (2) ;
15 join
16 e nd module
14 DPI (Direct Programming Inter-
face)
14.1 Importing C Functions
1 // C fun ct io n
2 im por t " DPI - C" f un ct ion int c_add (
3 input int a , input int b
4 ) ;
5
6 mo dul e dpi_ te st ;
7 ini ti al begin
8 int re sul t ;
9 resul t = c_a dd (5 , 3) ;
10 $ di sp la y (" Res ult = %0 d" , resu lt ) ;
11 end
12 e nd module
15 Advanced Memory Modeling
15.1 Associative Array with Methods
1 mo dul e mem_ mode l ;
2 int mem [ bit [15 :0 ]] ;
3
4 ini ti al begin
5 mem [16 ’ h00 00 ] = 32 ’ hD EA DBEEF ;
6 mem [16 ’ h01 00 ] = 32 ’ hC AF EBABE ;
7
8 // Iter at e
9 fore ac h ( mem [ addr ]) be gin
10 $ d is pl ay (" Addr =% h Data =% h" ,
11 addr , mem [ addr ]) ;
12 end
13
14 // Check e xi stenc e
15 if ( mem . ex ist s (16 ’ h 0000) )
16 $ d is pl ay (" A dd re ss exis ts " );
17
18 // Delet e
19 mem . del ete (16 ’ h0000 ) ;
20 $ di sp la y (" Size : %0 d" , mem . size () ) ;
21 end
22 e nd module
4
SystemVerilog Complete Reference Algo Science Lab
16 Practical Examples
16.1 FIFO Design
1 mo dul e fifo #(
2 pa ra meter DEPTH = 16 ,
3 pa ra meter WIDTH = 8
4 ) (
5 input logic clk , rst_n ,
6 input logic wr_en , rd_en ,
7 input logic [ WIDTH -1:0] wr_data ,
8 outp ut l ogic [ WIDTH -1:0] rd_data ,
9 outp ut l ogic full , empty
10 ) ;
11 logic [ WIDTH -1:0] mem [ DEPTH ];
12 logic [ $clog 2 ( DEPT H ):0] wr_ptr , rd_ptr ;
13
14 assi gn ful l = ( wr_p tr [ $ cl og2 ( D EPTH ) ] !=
15 rd_pt r [ $c lo g2 ( DE PTH ) ]) &&
16 ( wr_p tr [ $ clo g2 ( DE PTH ) -1:0]
==
17 rd_pt r [ $c lo g2 ( DE PTH ) -1:0]) ;
18 assi gn e mpty = ( wr_ ptr == rd_ptr );
19
20 al wa ys_ff @( posedge clk or ne ge dg e rs t_n )
begin
21 if (! r st_n ) begin
22 wr_ ptr <= ’0;
23 rd_ ptr <= ’0;
24 end else beg in
25 if ( wr_ en && ! full )
26 wr _pt r <= wr _p tr + 1;
27 if ( rd_ en && ! em pty )
28 rd _pt r <= rd _p tr + 1;
29 end
30 end
31
32 al wa ys_ff @( posedge clk ) be gin
33 if ( wr_en && ! full )
34 mem [ wr_p tr [ $ clo g2 ( D EPTH ) -1:0]] <=
35 wr _d at a ;
36 end
37
38 assi gn rd_dat a =
39 mem [ rd_ ptr [ $clog 2 ( DEPT H ) -1:0]];
40 e nd module
16.2 UART Transmitter
1 mo dul e uart_ tx #(
2 pa ra meter CL K_ FR EQ = 50 _000_000 ,
3 pa ra meter BA UD_RA TE = 115200
4 ) (
5 input logic clk , rst_n ,
6 input logic [7 :0] data ,
7 input logic start ,
8 outp ut l ogic tx ,
9 outp ut l ogic busy
10 ) ;
11 lo ca lpar am CL KS_P ER_B IT =
12 CLK _F RE Q / BAUD_ RATE ;
13
14 typ ed ef e num log ic [2 :0] {
15 IDLE , START , DATA , ST OP
16 } s ta te_ t ;
17
18 sta te _t state ;
19 logic [ 7:0] tx_ da ta ;
20 logic [ $clog 2 ( CLKS _PER _BIT ) -1:0] c lk _c nt ;
21 logic [ 2:0] bit _c nt ;
22
23 assi gn bus y = ( state != I DLE ) ;
24
25 al wa ys_ff @( posedge clk or ne ge dg e rs t_n )
begin
26 if (! r st_n ) begin
27 state <= IDLE ;
28 tx <= 1;
29 cl k_cnt <= 0;
30 bi t_cnt <= 0;
31 end else beg in
32 case ( state )
33 IDLE : begin
34 tx <= 1;
35 if ( st art ) begin
36 tx_d at a <= data ;
37 state <= START ;
38 clk_ cn t <= 0;
39 end
40 end
41
42 START : be gin
43 tx <= 0;
44 if ( c lk _c nt ==
CLKS_ PE R_B IT -1) begin
45 state <= DATA ;
46 clk_ cn t <= 0;
47 bit_ cn t <= 0;
48 end else
49 clk_ cn t <= clk_c nt +
1;
50 end
51
52 DATA : begin
53 tx <= t x_ data [ b it _c nt ];
54 if ( c lk _c nt ==
CLKS_ PE R_B IT -1) begin
55 clk_ cn t <= 0;
56 if ( bit _c nt == 7)
57 state <= STOP ;
58 else
59 bit _c nt <= bit_ cn t
+ 1;
60 end else
61 clk_ cn t <= clk_c nt +
1;
62 end
63
64 STOP : begin
65 tx <= 1;
66 if ( c lk _c nt ==
CLKS_ PE R_B IT -1)
67 state <= IDLE ;
68 else
69 clk_ cn t <= clk_c nt +
1;
70 end
71 en dcase
72 end
73 end
74 e nd module
Conclusion
This reference covers the essential SystemVerilog constructs for both RTL design and verification. SystemVerilog
combines the best of Verilog with modern programming concepts, making it the industry standard for digital
design and verification.
Algo Science Lab - SystemVerilog Reference v1.0
Author: Shahrear Hossain Shawon
5

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SystemVerilog Complete Reference Algo Science Lab
Complete SystemVerilog Reference Guide
Comprehensive Coverage with Examples
Author: Shahrear Hossain Shawon Algo Science Lab 1 Data Types 11
// A s s o c i a t i v e a r r a y 12
int a s s o c _ a r r [ s t r i n g ]; 1.1 Logic and Bit Types 13
SystemVerilog provides 4-state (0,1,X,Z) and 2-state14 // Queue 15 int q u e u e [ $ ];
(0,1) data types for hardware modeling. 16
q u e u e . p u s h _ b a c k (5) ; 1 // 4 - s t a t e t y p e s 2 l o g i c [ 7 : 0 ] d a t a ; // 8 - bit 3
l o g i c s i g n e d [ 1 5 : 0 ] s ; // s i g n e d 2 Modules and Interfaces 4
reg [ 3 : 0 ] o l d _ s t y l e ; // l e g a c y 5 2.1 Module with Parameters 6 // 2 - s t a t e t y p e s
Modules are the basic building blocks with optional pa- 7
bit [ 7 : 0 ] f a s t _ d a t a ;
// f a s t e r s i m u l a t i o n 8
b y t e s i g n e d _ b y t e ; // 8 - bit s i g n e d rameters for configurability. 9 s h o r t i n t si ; // 16 - bit s i g n e d 10 int i ; // 32 - bit s i g n e d 1 m o d u l e a d d e r #( 11 l o n g i n t li ; // 64 - bit s i g n e d 2
p a r a m e t e r W I D T H = 8 3 ) ( 4 i n p u t
l o g i c [ WIDTH - 1 : 0 ] a , b , 1.2 Enumerated Types 5 i n p u t l o g i c cin ,
Enumerations provide named values for better readabil- 6
o u t p u t l o g i c [ WIDTH - 1 : 0 ] sum , ity and type safety. 7 o u t p u t l o g i c c o u t 8 ) ; 9
a s s i g n { cout , sum } = a + b + cin ; 1
t y p e d e f e n u m l o g i c [ 1 : 0 ] { 10 e n d m o d u l e 2 I D L E = 2 ’ b00 , 3 R E A D = 2 ’ b01 , 4 W R I T E = 2 ’ b10 , 2.2 Interface 5 E R R O R = 2 ’ b11 6 } s t a t e _ t ;
Interfaces encapsulate communication signals between 7 modules. 8
s t a t e _ t c u r r e n t _ s t a t e , n e x t _ s t a t e ; 1
i n t e r f a c e a x i _ i f #( 1.3 Structures and Unions 2
p a r a m e t e r A D D R _ W I D T H = 32 ,
Structures group related data, unions save space by 3
p a r a m e t e r D A T A _ W I D T H = 32 4 ) ( overlapping members. 5
i n p u t l o g i c clk , r s t _ n 6 ) ; 1 // S t r u c t u r e 7
l o g i c [ A D D R _ W I D T H - 1 : 0 ] a w a d d r ; 2
t y p e d e f s t r u c t p a c k e d { 8
l o g i c awvalid , a w r e a d y ; 3
l o g i c [ 7 : 0 ] o p c o d e ; 9
l o g i c [ D A T A _ W I D T H - 1 : 0 ] w d a t a ; 4
l o g i c [ 1 5 : 0 ] a d d r ; 10
l o g i c wvalid , w r e a d y ; 5
l o g i c [ 3 1 : 0 ] d a t a ; 11 6 } i n s t r u c t i o n _ t ; 12 m o d p o r t m a s t e r ( 7 13
o u t p u t awaddr , awvalid , wdata , wvalid , 8
i n s t r u c t i o n _ t i n s t r ; 14 i n p u t awready , w r e a d y 9 15 ) ; 10 // U n i o n 16 11
t y p e d e f u n i o n p a c k e d { 17 m o d p o r t s l a v e ( 12
l o g i c [ 3 1 : 0 ] w o r d ; 18 i n p u t
awaddr , awvalid , wdata , wvalid , 13
l o g i c [ 1 5 : 0 ] h a l f [ 2 ] ; 19
o u t p u t awready , w r e a d y 14
l o g i c [ 7 : 0 ] b y t e [ 4 ] ; 20 ) ; 15 } d a t a _ u ; 21 e n d i n t e r f a c e 1.4 Arrays 2.3 Module with Interface
SystemVerilog supports packed, unpacked, dynamic, associative, and queue arrays. 1
m o d u l e a x i _ m a s t e r ( 1 // P a c k e d a r r a y 2 a x i _ i f . m a s t e r bus 2
l o g i c [ 7 : 0 ] [ 3 : 0 ] p a c k e d _ a r r ; 3 ) ; 3 4
a l w a y s _ f f @ ( p o s e d g e bus . clk ) b e g i n 4 // U n p a c k e d a r r a y 5 if (! bus . r s t _ n ) 5
l o g i c [ 7 : 0 ] mem [ 0 : 2 5 5 ] ; 6 bus . a w v a l i d <= 0; 6 7
e l s e if ( bus . a w r e a d y ) 7 // D y n a m i c a r r a y 8 bus . a w v a l i d <= 1; 8 int d y n _ a r r []; 9 end 9
i n i t i a l d y n _ a r r = new [ 1 0 ] ; 10 e n d m o d u l e 10 1
SystemVerilog Complete Reference Algo Science Lab 3 Sequential Logic 16 end 17 e n d m o d u l e 3.1 Always FF Blocks
Use always ff for synthesizable sequential logic. 5 State Machines 1 m o d u l e dff ( 5.1 FSM with Enum 2 i n p u t l o g i c clk , rst_n , 3 i n p u t l o g i c d ,
Finite state machines are fundamental in digital design. 4 o u t p u t l o g i c q 5 ) ; 1 m o d u l e fsm ( 6
a l w a y s _ f f @ ( p o s e d g e clk or n e g e d g e r s t _ n ) 2 i n p u t l o g i c clk , rst_n , b e g i n 3 i n p u t l o g i c start , done , 7 if (! r s t _ n ) 4 o u t p u t l o g i c b u s y 8 q <= 1 ’ b0 ; 5 ) ; 9 e l s e 6
t y p e d e f e n u m l o g i c [ 1 : 0 ] { 10 q <= d ; 7
IDLE , ACTIVE , WAIT , C O M P L E T E 11 end 8 } s t a t e _ t ; 12 e n d m o d u l e 9 10
s t a t e _ t state , n e x t ; 3.2 Counter Example 11 12 // S t a t e r e g i s t e r 13
a l w a y s _ f f @ ( p o s e d g e clk or n e g e d g e r s t _ n ) 1 m o d u l e c o u n t e r #( b e g i n 2
p a r a m e t e r W I D T H = 8 14 if (! r s t _ n ) 3 ) ( 15 s t a t e <= I D L E ; 4 i n p u t l o g i c clk , rst_n , en , 16 e l s e 5
o u t p u t l o g i c [ WIDTH - 1 : 0 ] c o u n t 17 s t a t e <= n e x t ; 6 ) ; 18 end 7
a l w a y s _ f f @ ( p o s e d g e clk or n e g e d g e r s t _ n ) 19 b e g i n 20 // N e x t s t a t e l o g i c 8 if (! r s t _ n ) 21
a l w a y s _ c o m b b e g i n 9 c o u n t <= ’0; 22 n e x t = s t a t e ; 10 e l s e if ( en ) 23 c a s e ( s t a t e ) 11 c o u n t <= c o u n t + 1; 24
I D L E : if ( s t a r t ) n e x t = A C T I V E ; 12 end 25
A C T I V E : n e x t = W A I T ; 13 e n d m o d u l e 26
W A I T : if ( d o n e ) n e x t = C O M P L E T E ; 27
C O M P L E T E : n e x t = I D L E ; 4 Combinational Logic 28 e n d c a s e 29 end 4.1 Always Comb Blocks 30 31 // O u t p u t l o g i c
Use always comb for combinational logic. 32
a s s i g n b u s y = ( s t a t e != I D L E ) ; 33 e n d m o d u l e 1 m o d u l e m u x 4 t o 1 ( 2 i n p u t l o g i c [ 1 : 0 ] sel , 3 i n p u t l o g i c [ 3 : 0 ] in , 6 Functions and Tasks 4 o u t p u t l o g i c out 5 ) ; 6.1 Functions 6
a l w a y s _ c o m b b e g i n 7 c a s e ( sel )
Functions return a single value and execute in zero sim- 8 2 ’ b00 : out = in [ 0 ] ; ulation time. 9 2 ’ b01 : out = in [ 1 ] ; 10 2 ’ b10 : out = in [ 2 ] ; 1
f u n c t i o n a u t o m a t i c int p a r i t y ( 11 2 ’ b11 : out = in [ 3 ] ; 2
i n p u t l o g i c [ 7 : 0 ] d a t a 12 e n d c a s e 3 ) ; 13 end 4
p a r i t y = ^ d a t a ; // XOR r e d u c t i o n 14 e n d m o d u l e 5 e n d f u n c t i o n 6 7
f u n c t i o n a u t o m a t i c l o g i c [ 7 : 0 ] r e v e r s e ( 4.2 Priority and Unique 8
i n p u t l o g i c [ 7 : 0 ] in
priority and unique provide synthesis and simulation 9 ) ; checks. 10 for ( int i =0; i <8; i ++) 11
r e v e r s e [ i ] = in [7 - i ]; 1 m o d u l e d e c o d e r ( 12 e n d f u n c t i o n 2 i n p u t l o g i c [ 2 : 0 ] in , 3
o u t p u t l o g i c [ 7 : 0 ] out 6.2 Tasks 4 ) ; 5
a l w a y s _ c o m b b e g i n
Tasks can have multiple outputs and consume simula- 6 u n i q u e c a s e ( in ) tion time. 7
3 ’ d0 : out = 8 ’ b 0 0 0 0 0 0 0 1 ; 8
3 ’ d1 : out = 8 ’ b 0 0 0 0 0 0 1 0 ; 1
t a s k a u t o m a t i c r e a d _ m e m ( 9
3 ’ d2 : out = 8 ’ b 0 0 0 0 0 1 0 0 ; 2 i n p u t l o g i c [ 7 : 0 ] addr , 10
3 ’ d3 : out = 8 ’ b 0 0 0 0 1 0 0 0 ; 3
o u t p u t l o g i c [ 3 1 : 0 ] data , 11
3 ’ d4 : out = 8 ’ b 0 0 0 1 0 0 0 0 ; 4 ref l o g i c [ 3 1 : 0 ] mem [] 12
3 ’ d5 : out = 8 ’ b 0 0 1 0 0 0 0 0 ; 5 ) ; 13
3 ’ d6 : out = 8 ’ b 0 1 0 0 0 0 0 0 ; 6 #10 d a t a = mem [ a d d r ]; 14
3 ’ d7 : out = 8 ’ b 1 0 0 0 0 0 0 0 ; 7 e n d t a s k 15 e n d c a s e 8 2
SystemVerilog Complete Reference Algo Science Lab 9
t a s k a u t o m a t i c w r i t e _ m e m ( 18 10
i n p u t l o g i c [ 7 : 0 ] addr , 19
f u n c t i o n v o i d d i s p l a y () ; 11
i n p u t l o g i c [ 3 1 : 0 ] data , 20
$display (" Addr =%h Data =%h Type =%b", 12 ref l o g i c [ 3 1 : 0 ] mem [] 21 addr , data , p t y p e ) ; 13 ) ; 22 e n d f u n c t i o n 14
#10 mem [ a d d r ] = d a t a ; 23 e n d c l a s s 15 e n d t a s k 24 25 m o d u l e t e s t ; 26 i n i t i a l b e g i n 7 Assertions 27 p a c k e t pkt = new () ; 28 r e p e a t (5) b e g i n 7.1 Immediate Assertions 29
a s s e r t ( pkt . r a n d o m i z e () ) ;
Checked immediately like a procedural statement. 30 pkt . d i s p l a y () ; 31 end 1
m o d u l e a s s e r t _ e x a m p l e ( 32 end 2
i n p u t l o g i c clk , rst_n , 33 e n d m o d u l e 3 i n p u t l o g i c req , gnt 4 ) ; 9 Coverage 5
// I m m e d i a t e a s s e r t i o n 6
a l w a y s _ c o m b b e g i n 9.1 Covergroups 7
a s s e r t (!( req && ! gnt ) || gnt ) 8
e l s e $error ( " Grant without request " ) ;
Functional coverage to track test completeness. 9 end 10 e n d m o d u l e 1
m o d u l e c o v e r a g e _ e x a m p l e ( 2 i n p u t l o g i c clk , 3
i n p u t l o g i c [ 2 : 0 ] opcode , 7.2 Concurrent Assertions 4
i n p u t l o g i c [ 7 : 0 ] d a t a
Checked based on clock edges, using sequences and 5 ); properties. 6
c o v e r g r o u p cg @ ( p o s e d g e clk ) ; 7
c p _ o p c o d e : c o v e r p o i n t o p c o d e { 1
m o d u l e s v a _ e x a m p l e ( 8
b i n s add = {3 ’ b 0 0 0 }; 2
i n p u t l o g i c clk , rst_n , 9
b i n s sub = {3 ’ b 0 0 1 }; 3
i n p u t l o g i c req , gnt , d o n e 10
b i n s mul = {3 ’ b 0 1 0 }; 4 ) ; 11
b i n s div = {3 ’ b 0 1 1 }; 5
// P r o p e r t y : g r a n t f o l l o w s r e q u e s t 12
b i n s o t h e r s = d e f a u l t ; 6
p r o p e r t y p _ r e q _ g n t ; 13 } 7
@ ( p o s e d g e clk ) d i s a b l e iff (! r s t _ n ) 14 8
req | - > # # [ 1 : 3 ] gnt ; 15
c p _ d a t a : c o v e r p o i n t d a t a { 9 e n d p r o p e r t y 16
b i n s low = { [ 0 : 6 3 ] } ; 10 17
b i n s mid = { [ 6 4 : 1 9 1 ] } ; 11
a s s e r t p r o p e r t y ( p _ r e q _ g n t ) 18
b i n s h i g h = { [ 1 9 2 : 2 5 5 ] } ; 12
e l s e $error ( " Grant not received " ) ; 19 } 13 20 14
// S e q u e n c e : d o n e a f t e r g r a n t 21
c r o s s _ o p _ d a t a : c r o s s c p _ o p c o d e , c p _ d a t a ; 15
s e q u e n c e s _ g n t _ d o n e ; 16 gnt # # [ 1 : 5 ] d o n e ; 22 e n d g r o u p 17 e n d s e q u e n c e 23 18 24 cg c g _ i n s t = new () ; 19 a s s e r t p r o p e r t y ( 25 e n d m o d u l e 20
@ ( p o s e d g e clk ) d i s a b l e iff (! r s t _ n ) 21
gnt | - > s _ g n t _ d o n e 10 Clocking Blocks 22 ) ; 23 e n d m o d u l e 10.1 Synchronous Testbench
Clocking blocks provide synchronous drive and sample 8 Constrained Random timing. 8.1 Classes with Constraints 1
i n t e r f a c e b u s _ i f ( i n p u t l o g i c clk ) ;
Object-oriented features for verification. 2 l o g i c [ 7 : 0 ] d a t a ; 3 l o g i c valid , r e a d y ; 1 c l a s s p a c k e t ; 4 2
r a n d bit [ 7 : 0 ] a d d r ; 5
c l o c k i n g cb @ ( p o s e d g e clk ) ; 3
r a n d bit [ 1 5 : 0 ] d a t a ; 6
d e f a u l t i n p u t #1 s t e p o u t p u t #2; 4
r a n d bit [ 1 : 0 ] p t y p e ; 7 o u t p u t data , v a l i d ; 5 8 i n p u t r e a d y ; 6
c o n s t r a i n t c _ a d d r { 9 e n d c l o c k i n g 7
a d d r i n s i d e {[8 ’ h00 :8 ’ h7F ]}; 10 8 } 11
m o d p o r t TB ( c l o c k i n g cb ) ; 9 12 e n d i n t e r f a c e 10
c o n s t r a i n t c _ t y p e { 13 11 p t y p e d i s t { 14
p r o g r a m t e s t ( b u s _ i f . TB bus ) ; 12 2 ’ b00 := 40 , 15 i n i t i a l b e g i n 13 2 ’ b01 := 30 , 16
bus . cb . d a t a <= 8 ’ hAA ; 14 2 ’ b10 := 20 , 17 bus . cb . v a l i d <= 1; 15 2 ’ b11 := 10 18 @ ( bus . cb ) ; 16 }; 19
w a i t ( bus . cb . r e a d y == 1) ; 17 } 20 end 3
SystemVerilog Complete Reference Algo Science Lab 21 e n d p r o g r a m 11 12
i n i t i a l b e g i n // C o n s u m e r 13 int d a t a ; 11 Virtual Interfaces 14 r e p e a t ( 1 0 ) b e g i n 15 mbx . get ( d a t a ) ; 11.1 Polymorphism in Verification 16
$display (" Received : %0d", data );
Virtual interfaces enable dynamic interface binding. 17 end 18 end 1 c l a s s d r i v e r ; 19 e n d m o d u l e 2
v i r t u a l b u s _ i f vif ; 3 13.2 Semaphore 4
f u n c t i o n new ( v i r t u a l b u s _ i f vif ) ; 5 t h i s . vif = vif ; 6 e n d f u n c t i o n 1
m o d u l e s e m a p h o r e _ e x a m p l e ; 7 2
s e m a p h o r e sem = new (1) ; 8 t a s k run () ; 3 9 f o r e v e r b e g i n 4
t a s k a c c e s s _ r e s o u r c e ( int id ) ; 10 @ ( vif . cb ) ; 5 sem . get () ; 11
vif . cb . d a t a <= $random ; 6
$display (" Task %0d accessing ", id); 12 vif . cb . v a l i d <= 1; 7 # 2 0 ; 13 @ ( vif . cb ) ; 8
$display (" Task %0d done ", id); 14 vif . cb . v a l i d <= 0; 9 sem . put () ; 15 end 10 e n d t a s k 16 e n d t a s k 11 17 e n d c l a s s 12 i n i t i a l f o r k 18 13
a c c e s s _ r e s o u r c e (1) ; 19 m o d u l e top ; 14
a c c e s s _ r e s o u r c e (2) ; 20 l o g i c clk ; 15 j o i n 21 b u s _ i f bus ( clk ) ; 16 e n d m o d u l e 22 23 i n i t i a l b e g i n 24
d r i v e r drv = new ( bus ) ; 14 DPI (Direct Programming Inter- 25 f o r k face) 26 drv . run () ; 27 j o i n _ n o n e 14.1 Importing C Functions 28 end 29 e n d m o d u l e 1 // C f u n c t i o n 2
i m p o r t " DPI - C " f u n c t i o n int c _ a d d ( 12 Parameterized Classes 3
i n p u t int a , i n p u t int b 4 ) ; 12.1 Generic Components 5 6 m o d u l e d p i _ t e s t ; 7 i n i t i a l b e g i n 1
c l a s s q u e u e #( t y p e T = int ) ; 8 int r e s u l t ; 2 T i t e m s [ $ ]; 9
r e s u l t = c _ a d d (5 , 3) ; 3 10
$display (" Result = %0d", result ); 4
f u n c t i o n v o i d p u s h ( T i t e m ) ; 11 end 5
i t e m s . p u s h _ b a c k ( i t e m ) ; 12 e n d m o d u l e 6 e n d f u n c t i o n 7 8 f u n c t i o n T pop () ; 15 Advanced Memory Modeling 9
r e t u r n i t e m s . p o p _ f r o n t () ; 10 e n d f u n c t i o n 15.1 Associative Array with Methods 11 12
f u n c t i o n int s i z e () ; 13
r e t u r n i t e m s . s i z e () ; 1
m o d u l e m e m _ m o d e l ; 14 e n d f u n c t i o n 2 int mem [ bit [ 1 5 : 0 ] ] ; 15 e n d c l a s s 3 16 4 i n i t i a l b e g i n 17 // U s a g e 5
mem [16 ’ h 0 0 0 0 ] = 32 ’ h D E A D B E E F ; 18
q u e u e #( int ) i n t _ q = new () ; 6
mem [16 ’ h 0 1 0 0 ] = 32 ’ h C A F E B A B E ; 19
q u e u e #( b y t e ) b y t e _ q = new () ; 7 8 // I t e r a t e 9
f o r e a c h ( mem [ a d d r ]) b e g i n 13 Interprocess Communication 10
$display (" Addr =%h Data =%h", 11 addr , mem [ a d d r ]) ; 13.1 Mailbox 12 end 13 1
m o d u l e i p c _ e x a m p l e ; 14 // C h e c k e x i s t e n c e 2
m a i l b o x #( int ) mbx = new () ; 15
if ( mem . e x i s t s (16 ’ h 0 0 0 0 ) ) 3 16 $display (" Address exists "); 4
i n i t i a l b e g i n // P r o d u c e r 17 5
for ( int i =0; i < 1 0 ; i ++) b e g i n 18 // D e l e t e 6 mbx . put ( i ) ; 19
mem . d e l e t e (16 ’ h 0 0 0 0 ) ; 7 $display (" Sent : %0d", i); 20
$display (" Size : %0d", mem . size ()); 8 # 1 0 ; 21 end 9 end 22 e n d m o d u l e 10 end 4
SystemVerilog Complete Reference Algo Science Lab 16 Practical Examples 18 s t a t e _ t s t a t e ; 19
l o g i c [ 7 : 0 ] t x _ d a t a ; 16.1 FIFO Design 20
l o g i c [ $clog2 ( C L K S _ P E R _ B I T ) -1:0] clk_cnt ; 21
l o g i c [ 2 : 0 ] b i t _ c n t ; 1 m o d u l e f i f o #( 22 2
p a r a m e t e r D E P T H = 16 , 23
a s s i g n b u s y = ( s t a t e != I D L E ) ; 3
p a r a m e t e r W I D T H = 8 24 4 ) ( 25
a l w a y s _ f f @ ( p o s e d g e clk or n e g e d g e r s t _ n ) 5 i n p u t l o g i c clk , rst_n , b e g i n 6 i n p u t l o g i c wr_en , rd_en , 26 if (! r s t _ n ) b e g i n 7 i n p u t
l o g i c [ WIDTH - 1 : 0 ] wr_data , 27 s t a t e <= I D L E ; 8
o u t p u t l o g i c [ WIDTH - 1 : 0 ] rd_data , 28 tx <= 1; 9
o u t p u t l o g i c full , e m p t y 29 c l k _ c n t <= 0; 10 ) ; 30 b i t _ c n t <= 0; 11
l o g i c [ WIDTH - 1 : 0 ] mem [ D E P T H ]; 31 end e l s e b e g i n 12
l o g i c [ $clog2 ( DEPTH ) :0] wr_ptr , rd_ptr ; 32 c a s e ( s t a t e ) 13 33 I D L E : b e g i n 14
a s s i g n f u l l = ( w r _ p t r [ $clog2 ( DEPTH ) ] != 34 tx <= 1; 15
r d _ p t r [ $clog2 ( DEPTH ) ]) && 35 if ( s t a r t ) b e g i n 16
( w r _ p t r [ $clog2 ( DEPTH ) -1:0] 36 t x _ d a t a <= d a t a ; == 37 s t a t e <= S T A R T ; 17
r d _ p t r [ $clog2 ( DEPTH ) -1:0]) ; 38 c l k _ c n t <= 0; 18
a s s i g n e m p t y = ( w r _ p t r == r d _ p t r ) ; 39 end 19 40 end 20
a l w a y s _ f f @ ( p o s e d g e clk or n e g e d g e r s t _ n ) 41 b e g i n 42 S T A R T : b e g i n 21 if (! r s t _ n ) b e g i n 43 tx <= 0; 22 w r _ p t r <= ’0; 44 if ( c l k _ c n t == 23 r d _ p t r <= ’0;
C L K S _ P E R _ B I T -1) b e g i n 24 end e l s e b e g i n 45 s t a t e <= D A T A ; 25
if ( w r _ e n && ! f u l l ) 46 c l k _ c n t <= 0; 26 w r _ p t r <= w r _ p t r + 1; 47 b i t _ c n t <= 0; 27
if ( r d _ e n && ! e m p t y ) 48 end e l s e 28 r d _ p t r <= r d _ p t r + 1; 49 c l k _ c n t <= c l k _ c n t + 29 end 1; 30 end 50 end 31 51 32
a l w a y s _ f f @ ( p o s e d g e clk ) b e g i n 52 D A T A : b e g i n 33
if ( w r _ e n && ! f u l l ) 53
tx <= t x _ d a t a [ b i t _ c n t ]; 34
mem [ w r _ p t r [ $clog2 ( DEPTH ) -1:0]] <= 54 if ( c l k _ c n t == 35 w r _ d a t a ;
C L K S _ P E R _ B I T -1) b e g i n 36 end 55 c l k _ c n t <= 0; 37 56 if ( b i t _ c n t == 7) 38 a s s i g n r d _ d a t a = 57 s t a t e <= S T O P ; 39
mem [ r d _ p t r [ $clog2 ( DEPTH ) -1:0]]; 58 e l s e 40 e n d m o d u l e 59 b i t _ c n t <= b i t _ c n t + 1; 16.2 UART Transmitter 60 end e l s e 61 c l k _ c n t <= c l k _ c n t + 1; 1 m o d u l e u a r t _ t x #( 62 end 2
p a r a m e t e r C L K _ F R E Q = 50 _ 0 0 0 _ 0 0 0 , 63 3
p a r a m e t e r B A U D _ R A T E = 1 1 5 2 0 0 64 S T O P : b e g i n 4 ) ( 65 tx <= 1; 5 i n p u t l o g i c clk , rst_n , 66 if ( c l k _ c n t == 6 i n p u t l o g i c [ 7 : 0 ] data , C L K S _ P E R _ B I T -1) 7 i n p u t l o g i c start , 67 s t a t e <= I D L E ; 8 o u t p u t l o g i c tx , 68 e l s e 9 o u t p u t l o g i c b u s y 69 c l k _ c n t <= c l k _ c n t + 10 ) ; 1; 11
l o c a l p a r a m C L K S _ P E R _ B I T = 70 end 12
C L K _ F R E Q / B A U D _ R A T E ; 71 e n d c a s e 13 72 end 14
t y p e d e f e n u m l o g i c [ 2 : 0 ] { 73 end 15 IDLE , START , DATA , S T O P 74 e n d m o d u l e 16 } s t a t e _ t ; 17 Conclusion
This reference covers the essential SystemVerilog constructs for both RTL design and verification. SystemVerilog
combines the best of Verilog with modern programming concepts, making it the industry standard for digital design and verification.
Algo Science Lab - SystemVerilog Reference v1.0
Author: Shahrear Hossain Shawon 5

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