Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Lecture 12:
MOS Transistor Models
Prof. Niknejad
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Lecture Outline
MOS Transistors (4.3 – 4.6)
I-V curve (Square-Law Model)
Small Signal Model (Linear Model)
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Observed Behavior: I
D
-V
GS
Current zero for negative gate voltage
Current in transistor is very low until the gate
voltage crosses the threshold voltage of device
(same threshold voltage as MOS capacitor)
Current increases rapidly at first and then it finally
reaches a point where it simply increases linearly
G
S
V
DS
I
T
V
GS
V
DS
I
DS
V
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Observed Behavior: I
D
-V
DS
For low values of drain voltage, the device is like a resistor
As the voltage is increases, the resistance behaves non-linearly
and the rate of increase of current slows
Eventually the current stops growing and remains essentially
constant (current source)
DS
V
/
DS
Ik
“constant” current
resistor region
non-linear resistor region
2
GS
V
V=
3
GS
V
V=
4
GS
V
V=
G
S
V
DS
I
DS
V
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
“Linear” Region Current
If the gate is biased above threshold, the surface is
inverted
This inverted region forms a channel that connects
the drain and gate
If a drain voltage is applied positive, electrons will
flow from source to drain
p-type
n+
n+
p+
Inversion layer
“channel”
GS Tn
VV>
1
00mV
DS
V
G
D
S
NMOS
x
y
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
MOSFET: Variable Resistor
Notice that in the linear region, the current is
proportional to the voltage
Can define a voltage-dependent resistor
This is a nice variable resistor, electronically
tunable!
(
)
DS n ox GS Tn DS
W
ICVVV
L
µ
=−
1
(
)
()
DS
eq GS
DS n ox GS Tn
V
LL
RRV
ICVVW W
µ

== =


Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Finding I
D
= f (V
GS
, V
DS
)
Approximate inversion charge Q
N
(y): drain is
higher than the source less charge at drain end
of channel
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Inversion Charge at Source/Drain
(
0
)( Ly
Q
y
Q
yQ
NNN
=+=
)
(
)0(
T
n
G
SoxN
V
V
CyQ ==
==
)
(
LyQ
N
)
(
T
n
G
D
o
x
V
V
C
DS
G
S
G
D
V
V
=
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Average Inversion Charge
Charge at drain end is lower since field is lower
Simple approximation: In reality we should
integrate the total charge minus the bulk depletion
charge across the channel
(
)( )
()
2
o
xGS T oxGD T
N
C
VVCVV
Qy
−+
≈−
Source End Drain End
(
)( )
()
2
o
x GS T ox GS SD T
N
C
VVCVVV
Qy
−+
≈−
(2 2 )
() ( )
2
2
ox GS T ox SD DS
NoxGST
CV V CV V
Qy CV V
−−
≈− =−
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Drift Velocity and Drain Current
Long-channel” assumption: use mobility to find v
() () ( / )
n
DS
nn
V
vy Ey V y
L
µ
µµ
=− ≈− =
Substituting:
()
2
DS DS
DN oxGST
VV
IWvQW CVV
L
µ
=−
(
)
2
DS
DoxGSTDS
V
W
ICVVV
L
µ
≈−
Inverted Parabolas
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Square-Law Characteristics
Boundary: what is I
D,SAT
?
TRIODE REGION
SATURATION REGION
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
The Saturation Region
When V
DS
> V
GS
–V
Tn
, there isn’t any inversion
charge at the drain … according to our simplistic model
Why do curves
flatten out?
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Square-Law Current in Saturation
Current stays at maximum (where V
DS
= V
GS
V
Tn
= V
DS,SAT
)
Measurement: I
D
increases slightly with increasing V
DS
model with linear “fudge factor”
(
)
2
DS
DoxGSTDS
V
W
ICVVV
L
µ
=−
,
(
)( )
2
GS T
DS sat ox GS T GS T
VV
W
ICVV VV
L
µ
=−
2
,
(
)
2
ox
DS sat GS T
C
W
IVV
L
µ
=−
2
,
(
)(1 )
2
ox
DS sat GS T DS
C
W
IVVV
L
µ
λ
=−+
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Pinching the MOS Transistors
When V
DS
> V
DS,sat
, the channel is “pinched” off at drain end (hence the
name “pinch-off region”)
Drain mobile charge goes to zero (region is depleted), the remaining elecric
field is dropped across this high-field depletion region
As the drain voltage is increases further, the pinch off point moves back
towards source
Channel Length Modulation: The effective channel length is thus reduced
higher I
DS
p-type
n+
n+
p+
Pinch-Off Point
G
STn
V
V>
DS
V
G
D
S
NMOS
Depletion Region
G
STn
V
V
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Linear MOSFET Model
Channel (inversion) charge: neglect reduction at drain
Velocity saturation defines V
DS,SAT
=E
sat
L = constant
-v
sat
/ µ
n
Drain current:
)
],
(
)
[
(
, TnGSoxsatNSATD
V
V
C
v
W
WvQI ==
|E
sat
| = 10
4
V/cm, L = 0.12 µm V
DS,SAT
= 0.12 V!
)
1
)
(
(
, DSnTnGSoxsatSATD
V
V
V
W
C
v
I
λ
+=
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Why Find an Incremental Model?
Signals of interest in analog ICs are often of the
form:
Direct substitution into i
D
= f(v
GS
, v
DS
) is
tedious AND doesnt include charge-storage
effects pretty rough approximation
(
)()
GS GS gs
vtV vt=+
Fixed Bias Point
Small Signal
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Which Operating Region?
3
V
GS
V =
3
V
DS
V =
TRIODE
SAT
OFF
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Changing One Variable at a Time
Assumption: V
DS
> V
DS,SAT
= V
GS
V
Tn
(square law)
G
S
V
/
DS
Ik
3
V
DS
V =
1
V
T
V =
Square Law
Saturation
Region
Linear
Triode
Region
Slope of Tangent: Incremental current increase
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
The Transconductance g
m
Defined as the change in drain current due to a change in the
gate-source voltage, with everything else constant
,,
()(1)
GS DS GS DS
DD
moxGSTDS
GS GS
VV VV
ii W
gCVVV
vv L
µλ
∆∂
=== +
∆∂
2
,
(
)(1 )
2
ox
DS sat GS T DS
C
W
IVVV
L
µ
λ
=−+
(
)
m
ox GS T
W
gCVV
L
µ
=−
0
2
2
DS
mox oxDS
ox
I
WW
gC CI
W
LL
C
L
µµ
µ
==
2
(
)
DS
m
G
ST
I
g
V
V
=
Gate Bias
Drain Current Bias
Drain Current Bias and
Gate Bias
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Output Resistance r
o
Defined as the inverse of the change in drain current due
to a change in the drain-source voltage, with everything
else constant
Non-Zero Slope
DS
V
δ
DS
I
δ

Preview text:

EECS 105 Fall 2003, Lecture 12 Lecture 12: MOS Transistor Models Prof. Niknejad Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Lecture Outline MOS Transistors (4.3 – 4.6)
– I-V curve (Square-Law Model)
– Small Signal Model (Linear Model) Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Observed Behavior: I -V D GS IDS IDS VDS VGS VGS VT
Current zero for negative gate voltage
Current in transistor is very low until the gate
voltage crosses the threshold voltage of device
(same threshold voltage as MOS capacitor)
Current increases rapidly at first and then it finally
reaches a point where it simply increases linearly Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Observed Behavior: I -V D DS I / k V = 4V DS GS non-linear resistor region IDS “constant” current VDS V = 3V GS resistor region VGS V = 2V GS VDS
For low values of drain voltage, the device is like a resistor
As the voltage is increases, the resistance behaves non-linearly
and the rate of increase of current slows
Eventually the current stops growing and remains essentially constant (current source) Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
“Linear” Region Current V > V GS Tn G S V D ≈100mV DS y p+ n+ n+ x p-type Inversion layer NMOS “channel”
If the gate is biased above threshold, the surface is inverted
This inverted region forms a channel that connects the drain and gate
If a drain voltage is applied positive, electrons will flow from source to drain Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
MOSFET: Variable Resistor
Notice that in the linear region, the current is proportional to the voltage W I =
µ C (V V )V DS n ox GS Tn DS L
Can define a voltage-dependent resistor V 1  L L DS R = = = R (V ) eq   I
µ C (V V ) GSW W DS n ox GS Tn
This is a nice variable resistor, electronically tunable! Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Finding I = f (V , V ) D GS DS
Approximate inversion charge Q (y): drain is N
higher than the source less charge at drain end of channel Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Inversion Charge at Source/Drain
Q ( y) ≈ Q ( y = 0) + Q ( y = L) N N N
Q ( y = 0) = C − (VV ) Q ( y N = L) = N ox GS TnC (VV ) ox GD Tn = GD G VS VDS Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Average Inversion Charge Source End Drain End C (V
V ) + C (V V ) Q ( y) ox GS T ox GD T ≈ − N 2 C (V
V ) + C (V V V ) Q ( y) ox GS T ox GS SD T ≈ − N 2 C (2V − 2V ) − C V V Q ( y) ox GS T ox SD ≈ − = −C ( DS VV − ) N 2 ox GS T 2
Charge at drain end is lower since field is lower
Simple approximation: In reality we should
integrate the total charge minus the bulk depletion charge across the channel Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Drift Velocity and Drain Current
“Long-channel” assumption: use mobility to find v µ V
v( y) = −µ E( y) ≈ −µ (− V ∆ / y ∆ ) n DS = n n L Substituting: V V DS I = WvQ W µ C ( DS VV − ) D N ox GS T L 2 W V I ≈ µC ( DS VV − )V D ox GS T L 2 DS Inverted Parabolas Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Square-Law Characteristics Boundary: what is I ? D,SAT TRIODE REGION SATURATION REGION Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad The Saturation Region When V > V
– V , there isn’t any inversion DS GS Tn
charge at the drain … according to our simplistic model Why do curves flatten out? Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Square-Law Current in Saturation
Current stays at maximum (where V = VV = V ) DS GS Tn DS,SAT W V I = µC ( DS VV − )V D ox GS T L 2 DS W V V I µ − = C ( GS T VV − )(VV ) DS ,sat ox GS T L 2 GS T W µCox 2 I = (VV ) DS ,sat L 2 GS T
Measurement: I increases slightly with increasing V D DS
model with linear “fudge factor” W µCox 2 I = (VV ) (1+ V λ ) DS ,sat L 2 GS T DS Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Pinching the MOS Transistors V > V GS Tn G S V D DS p+ n+ n+ VV GS Tn Depletion Region p-type NMOS Pinch-Off Point When V > V
, the channel is “pinched” off at drain end (hence the DS DS,sat name “pinch-off region”)
Drain mobile charge goes to zero (region is depleted), the remaining elecric
field is dropped across this high-field depletion region
As the drain voltage is increases further, the pinch off point moves back towards source
Channel Length Modulation: The effective channel length is thus reduced higher IDS Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Linear MOSFET Model
Channel (inversion) charge: neglect reduction at drain
Velocity saturation defines V = E L = constant DS,SAT sat - v / µ sat n Drain current: I = WvQ = W − (v )[ C − (VV )], D,SAT N sat ox GS Tn
|E | = 104 V/cm, L = 0.12 µm V sat DS,SAT = 0.12 V! I
= v WC (V V ) 1 ( + λ V ) D,SAT sat ox GS Tn n DS Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Why Find an Incremental Model?
Signals of interest in analog ICs are often of the form: v (t) = V + v (t) GS GS gs Fixed Bias Point Small Signal
Direct substitution into i = f(v , v ) is D GS DS
tedious AND doesn’t include charge-storage
effects … pretty rough approximation Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad Which Operating Region? V = 3V GS TRIODE V = 3V DS SAT OFF Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Changing One Variable at a Time I / k DS Linear V = 3V Triode DS Square Law Region Saturation V = 1V T Region
Slope of Tangent: Incremental current increase VGS Assumption: V > V = VV (square law) DS DS,SAT GS Tn Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
The Transconductance gm
Defined as the change in drain current due to a change in the
gate-source voltage, with everything else constant W µCox 2 I = (VV ) (1+ V λ ) DS ,sat L 2 GS T DS ≈ 0 iiW D D g = = = µC (VV )(1+ V λ ) m ox GS T DS vvL GS GS G V S , DS V GS V , DS V W g = µC (VV ) m ox GS T L Gate Bias W 2I W DS g = µC = 2µC I Drain Current Bias m ox ox DS L W L µCox L 2IDS g = m Drain Current Bias and (VV ) GS T Gate Bias Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad
Output Resistance ro
Defined as the inverse of the change in drain current due
to a change in the drain-source voltage, with everything else constant Non-Zero Slope δ IDS δVDS Department of EECS
University of California, Berkeley